1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device having a clamping circuit for making a drain voltage of a memory cell a desired voltage or lower when the memory cell is read out.
2. Description of the Related Art
In a nonvolatile semiconductor memory device, when a drain voltage of a memory cell is high when the memory cell is read out, a threshold value of the memory cell fluctuates, which is a cause of a data read error. Therefore, it is necessary that the drain voltage of the memory cell in readout be clamped to a voltage or lower at which the threshold voltage of the memory cell does not fluctuate.
FIG. 3 is a circuit diagram of a readout circuit of a conventional nonvolatile semiconductor memory device. The readout circuit illustrated in FIG. 3 includes a memory cell 101, a selection NMOS transistor 102, a clamp NMOS transistor 103, an NMOS transistor 301 forming an inverting amplifier, a constant current source 302, and a sense amplifier circuit 104.
A source of the memory cell 101 is connected to a ground terminal, a drain of the memory cell 101 is connected to a source of the selection NMOS transistor 102, and a gate of the memory cell 101 is connected to a CGBIAS terminal for inputting readout gate potential. A drain of the selection NMOS transistor 102 is connected to a source of the clamp NMOS transistor 103 and to a gate of the NMOS transistor 301, and a selection signal SG for selecting a memory cell to be read out is input to a gate of the selection NMOS transistor 102. The clamp NMOS transistor 103 is provided between the sense amplifier circuit 104 and the selection NMOS transistor 102, and a gate of the clamp NMOS transistor 103 is connected to a drain of the NMOS transistor 301. In the inverting amplifier, the constant current source 302 and the NMOS transistor 301 are connected in series between a power source terminal and a ground terminal. An input terminal of the sense amplifier circuit 104 is connected to a drain of the clamp NMOS transistor 103 (see Japanese Patent Application Laid-open No. 2001-250391, for example).
In the readout circuit as described above, the drain of the selection NMOS transistor 102 is clamped to a threshold voltage of the NMOS transistor 301, and hence, when the selection NMOS transistor 102 is turned ON, the drain voltage of the memory cell 101 is also clamped to the threshold voltage of the NMOS transistor 301. Further, by controlling the gate voltage of the clamp NMOS transistor 103 by the inverting amplifier, the source voltage of the clamp NMOS transistor 103 is controlled to be the above-mentioned voltage, and thus, the clamp voltage does not fluctuate depending on the amount of a current flowing through the memory cell 101.
FIG. 4 is a circuit diagram of a readout circuit of another conventional nonvolatile semiconductor memory device. In the readout circuit illustrated in FIG. 4, instead of the inverting amplifier illustrated in FIG. 3, a bias voltage BIAS is input to the gate of the clamp NMOS transistor 103 so as to obtain a desired clamp voltage (see Japanese Patent Application Laid-open No. Hei 05-36288).
In the readout circuit as described above, the drain voltage of the memory cell is clamped to substantially a voltage which is the bias voltage BIAS minus the threshold value of the clamp NMOS transistor 103.
However, in the conventional nonvolatile semiconductor memory device illustrated in FIG. 3, the inverting amplifier is used to control the clamp voltage as described above, and hence it takes time from when the selection NMOS transistor 102 is turned ON to when the clamp voltage is controlled to be the true clamp voltage. More specifically, it takes time from when the readout is started to when the drain voltage of the memory cell 101 becomes the true value, and thus, it takes time before the current flowing through the memory cell 101 to be read out becomes the true value. As a result, it takes time when the readout is started to when the true result of determination is output from the sense amplifier circuit.
Further, the conventional nonvolatile semiconductor memory device illustrated in FIG. 4 has a problem that the clamp voltage varies depending on the amount of a current flowing through the memory cell to be read out. For example, when a current flows through the memory cell, if the bias voltage BIAS is 1.2 V and the threshold value of the clamp NMOS transistor 103 is 0.5 V, the clamp voltage is 0.7 V. On the other hand, when a current does not flow through the memory cell and the conditions are the same as the above-mentioned conditions, the clamp voltage becomes as high as about 1.2 V, and the threshold value of the memory cell to be read out fluctuates. Therefore, even when a current does not flow through the memory cell, in order to attain the clamp voltage of 0.7 V, it is necessary to lower the bias voltage BIAS to about 0.7 V, and it follows that the clamp voltage when a current flows through the memory cell is 0.2 V, which is very low. As a result, the drain voltage of the memory cell through which a current flows is as low as 0.2 V and the value of a current flowing through the memory cell becomes small. Therefore, the speed of determination by the sense amplifier circuit for sensing the current flowing through the memory cell is lowered.
As described above, the conventional nonvolatile semiconductor memory devices illustrated in FIGS. 3 and 4 have a problem that it takes time from when the readout is started to when the sense amplifier circuit determines the current value of the memory cell.